1 Digital Design Using VHDL and PLDs1
1.1
VHDL/PLD Design Methodology1
1.2
Requirements Analysis and Specification5
1.3
VHDL Design Description6
1.4
Verification Using Simulation11
1.5
Testbenches13
1.6
Functional (Behavioral) Simulation16
1.7
Programmable Logic Devices (PLDs)18
1.8
SPLDs and the 22V1021
1.9
Logic Synthesis for the Target PLD27
1.10
Place-and-Route and Timing Simulation31
1.11
Programming and Verifying a Target PLD37
1.12
VHDL/PLD Design Methodology Advantages38
1.13
VHDL’s Development39
1.14
VHDL for Synthesis versus VHDL for Simulation39
1.15
This Book’s Primary Objective40
2 Entities , Architectures , and Coding Styles 44
2.1 Design Units, Library Units, and Design Entities44
2.2
Entity Declaration45
2.3
VHDL Syntax Definitions47
2.4
Port Modes50
2.5
Architecture Body53
2.6
Coding Styles55
2.7
Synthesis Results versus Coding Style66
2.8
Levels of Abstraction and Synthesis69
2.9
Design Hierarchy and Structural Style71
3 Signals and Data Types82
3.1
Object Classes and Object Types82
3.2
Signal Objects84
3.3
Scalar Types88
3.4
Type Std_Logic93
3.5
Scalar Literals and Scalar Constants99
3.6
Composite Types100
3.7
Arrays101
3.8
Types Unsigned and Signed107
3.9
Composite Literals and Composite Constants110
3.10
Integer Types112
3.11
Port Types for Synthesis116
3.12
Operators and Expressions118
4 Dataf low Style Combinational Design123
4.1
Logical Operators123
4.2
Signal Assignments in Dataflow Style Architectures127
4.3
Selected Signal Assignment130
4.4
Type Boolean and the Relational Operators132
4.5
Conditional Signal Assignment134
4.6
Priority Encoders139
4.7
Don’t Care Inputs and Outputs140
4.8
Decoders144
4.9
Table Lookup147
4.10
Three-state Buffers151
4.11
Avoiding Combinational Loops155
5 Behavi oral Style Combinational Design 165
5.1 Behavioral Style Architecture165
5.2
Process Statement169
5.3
Sequential Statements 170
5.4
Case Statement171
5.5
If Statement176
5.6
Loop Statement181
5.7
Variables185
5.8
Parity Detector Example188
5.9
Synthesis of Processes Describing Combinational Systems193
6 Event-Driven Simulation201
6.1
Simulator Approaches201
6.2
Elaboration203
6.3
Signal Drivers208
6.4
Simulator Kernel Process210
6.5
Simulation Initialization212
6.6
Simulation Cycles215
6.7
Signals versus Variables223
6.8
Delta Delays230
6.9
Delta Delays and Combinational Feedback235
6.10
Multiple Drivers239
6.11
Signal Attributes241
7 Testbenche s for Combinational Designs251
7.1
Design Verification251
7.2
Functional Verification of Combinational Designs255
7.3
A Simple Testbench255
7.4
Physical Types258
7.5
Single Process Testbench260
7.6
Wait Statements263
7.7
Assertion and Report Statements265
7.8
Records and Table Lookup Testbenches268
7.9
Testbenches That Compute Stimulus and Expected Results272
7.10
Predefined Shift Operators274
7.11
Stimulus Order Based on UUT Functionality276
7.12
Comparing a UUT to a Behavioral Intent Model279
7.13
Code Coverage and Branch Coverage281
7.14
Post-Synthesis and Timing Verifications for Combinational
Designs284
7.15
Timing Models Using VITAL and SDF288
8 Latches and Flip – flops304
8.1
Sequential Systems and Their Memory Elements304
8.2
D Latch308
8.3
Detecting Clock Edges315
8.4
D Flip-flops317
8.5
Enabled (Gated) Flip-flop324
8.6
Other Flip-flop Types328
8.7
PLD Primitive Memory Elements331
8.8
Timing Requirements and Synchronous Input Data332
9 MultibitLatches, Registers, Counters,
and Memory337
9.1
Multibit Latches and Registers337
9.2
Shift Registers340
9.3
Shift Register Counters346
9.4
Counters348
9.5
Detecting Non-clock Signal Edges360
9.6
Microprocessor Compatible Pulse Width Modulated Signal
Generator366
9.7
Memories370
10 Finite State Machines380
10.1
Finite State Machines380
10.2
FSM State Diagrams386
10.3
Three Process FSM VHDL Template388
10.4
State Diagram Development392
10.5
Decoder for an Optical Shaft Encoder403
10.6
State Encoding and State Assignment409
10.7
Supposedly Safe FSMs414
10.8
Inhibit Logic FSM Example418
10.9
Counters as Moore FSMs422
11 ASM Charts and RTL Design431
11.1
Algorithmic State Machine Charts431
11.2
Converting ASM Charts to VHDL43
11.3
System Architecture441
11.4
Successive Approximation Register Design Example445
11.5
Sequential Multiplier Design457
12 Subprograms469
12.1
Subprograms469
12.2
Functions473
12.3
Procedures480
12.4
Array Attributes and Unconstrained Arrays484
12.5
Overloading Subprograms and Operators491
12.6
Type Conversions494
13 Packages501
13.1
Packages and Package Bodies501
13.2
Standard and De Facto Standard Packages505
13.3
Package STD_LOGIC_1164510
13.4
Package NUMERIC_STD (IEEE Std 1076.3)516
13.5
Package STD_LOGIC_ARITH523
13.6
Packages for VHDL Text Output524
14 Testbenches for Sequential Systems526
14.1
Simple Sequential Testbenches526
14.2
Generating a System Clock527
14.3
Generating the System Reset531
14.4
Synchronizing Stimulus Generation and Monitoring532
14.5
Testbench for Successive Approximation Register538
14.6
Determining a Testbench Stimulus for a Sequential System542
14.7
Using Procedures for Stimulus Generation545
14.8
Output Verification in Stimulus Procedures550
14.9
Bus Functional Models552
14.10
Response Monitors560
15 Modular Design and Hierarchy566
15.1
Modular Design, Partitioning, and Hierarchy566
15.2
Design Units and Library Units571
15.3
Design Libraries573
15.4
Using Library Units574
15.5
Direct Design Entity Instantiation 577
15.6
Components and Indirect Design Entity Instantiation580
15.7Configuration Declarations587
15.8
Component Connections594
15.9
Parameterized Design Entities598
15.10
Library of Parameterized Modules (LPM)602
15.11
Generate Statement605
16 More Design Examples615
16.1
Microprocessor Compatible Quadrature
Decoder/Counter Design615
16.2
Verification of Quadrature Decoder/Counter624
16.3
Parameterized Quadrature Decoder/Counter628
16.4
Electronic Safe Design630
16.5
Verification of Electronic Safe644
16.6
Encoder for RF Transmitter Design649
Appendix VHDL Attributes659
Bibliography663
Index
