Fundamentals of Logic Design 7th Edition Roth Solutions Manual

Fundamentals of Logic Design 7th Edition Roth Solutions Manual

Product details:

• ISBN-10 ‏ : ‎ 1133628478
• ISBN-13 ‏ : ‎ 978-1133628477
• Author: Charles Roth

Updated with modern coverage, a streamlined presentation, and excellent companion software, this seventh edition of FUNDAMENTALS OF LOGIC DESIGN achieves yet again an unmatched balance between theory and application. Authors Charles H. Roth, Jr. and Larry L. Kinney carefully present the theory that is necessary for understanding the fundamental concepts of logic design while not overwhelming students with the mathematics of switching theory. Divided into 20 easy-to-grasp study units, the book covers such fundamental concepts as Boolean algebra, logic gates design, flip-flops, and state machines. By combining flip-flops with networks of logic gates, students will learn to design counters, adders, sequence detectors, and simple digital systems. After covering the basics, this text presents modern design techniques using programmable logic devices and the VHDL hardware description language.

Table contents:

• Chapter 1: Introduction Number Systems and Conversations
  • 1.1: Digital Systems and Switching Circuits
  • 1.2: Number Systems and Conversion (12)
  • 1.3: Binary Arithmetic (4)
  • 1.4: Representation of Negative Numbers (5)
  • 1.5: Binary Codes (8)
  • 1: Problems
  • 1: Chapter Quiz (19)
• Chapter 2: Boolean Algebra
  • 2.1: Introduction
  • 2.2: Basic Operations
  • 2.3: Boolean Expressions and Truth Tables (3)
  • 2.4: Basic Theorems
  • 2.5: Thermal Commutative, Associative, Distributive, and DeMorgan’s Laws (2)
  • 2.6: Simplification Theorems (12)
  • 2.7: Multiplying Out and Factoring (6)
  • 2.8: Complementing Boolean Expressions
  • 2: Problems
  • 2: Chapter Quiz (18)
• Chapter 3: Boolean Algebra (Continued)
  • 3.1: Multiplying Out and Factoring Expressions (4)
  • 3.2: Exclusive-OR and Equivalence Operations
  • 3.3: The Consensus Theorem (2)
  • 3.4: Algebraic Simplification of Switching Expressions (10)
  • 3.5: Proving Validity of an Equation (2)
  • 3: Problems
  • 3: Chapter Quiz (18)
• Chapter 4: Applications of Boolean Algebra Minterm and Maxterm Expansions
  • 4.1: Conversion of English Sentences to Boolean Equations (4)
  • 4.2: Combinational Logic Design Using a Truth Table (5)
  • 4.3: Minterm and Maxterm Expansions (4)
  • 4.4: General Minterm and Maxterm Expansions (6)
  • 4.5: Incompletely Specified Functions (3)
  • 4.6: Examples of Truth Table Construction (6)
  • 4.7: Design of Binary Adders and Subtracters
  • 4: Problems
  • 4: Chapter Quiz (18)
• Chapter 5: Karnaugh Maps
  • 5.1: Minimum Forms of Switching Functions
  • 5.2: Two- and Three-Variable Karnaugh Maps (5)
  • 5.3: Four-Variable Karnaugh Maps (8)
  • 5.4: Determination of Minimum Expressions Using Essential Prime Implicants (6)
  • 5.5: Five-Variable Karnaugh Maps (4)
  • 5.6: Other Uses of Karnaugh Maps
  • 5.7: Other Forms of Karnaugh Maps
  • 5: Problems
  • 5: Chapter Quiz (20)
• Chapter 6: Quine-McCluskey Method
  • 6.1: Determination of Prime Implicants (7)
  • 6.2: The Prime Implicant Chart (5)
  • 6.3: Petrick’s Method (2)
  • 6.4: Simplification of Incompletely Specified Functions
  • 6.5: Simplification Using Map-Entered Variables (1)
  • 6.6: Conclusion
  • 6: Problems
  • 6: Chapter Quiz (18)
• Chapter 7: Multi-Level Gate Circuits NAND and NOR Gates
  • 7.1: Multi-Level Gate Circuits (6)
  • 7.2: NAND and NOR Gates (1)
  • 7.3: Design of Two-Level NAND- and NOR-Gate Circuits (10)
  • 7.4: Design of Multi-Level NAND- and NOR-Gate Circuits
  • 7.5: Circuit Conversion Using Alternative Gate Symbols (13)
  • 7.6: Design of Two-Level, Multiple-Output Circuits
  • 7.7: Multiple-Output NAND- and NOR-Gate Circuits
  • 7: Problems
  • 7: Chapter Quiz (20)
• Chapter 8: Combinational Circuit Design and Simulation Using Gates
  • 8.1: Review of Combinational Circuit Design
  • 8.2: Design of Circuits with Limited Gate Fan-In
  • 8.3: Gate Delays and Timing Diagrams (3)
  • 8.4: Hazards in Combinational Logic (6)
  • 8.5: Simulation and Testing of Logic Circuits (2)
  • 8: Problems
  • 8: Chapter Quiz (18)
• Chapter 9: Multiplexers, Decoders, and Programmable Logic Devices
  • 9.1: Introduction
  • 9.2: Multiplexers (10)
  • 9.3: Three-State Buffers
  • 9.4: Decoders and Encoders (6)
  • 9.5: Read-Only Memories
  • 9.6: Programmable Logic Devices (5)
  • 9.7: Complex Programmable Logic Devices
  • 9.8: Field-Programmable Gate Arrays (4)
  • 9: Problems
  • 9: Chapter Quiz (18)
• Chapter 10: Introduction to VHDL
  • 10.1: VHDL Description of Combinational Circuits (3)
  • 10.2: VHDL Models for Multiplexers (1)
  • 10.3: VHDL Modules (1)
  • 10.4: Signals and Constants
  • 10.5: Arrays
  • 10.6: VHDL Operators (2)
  • 10.7: Packages and Libraries
  • 10.8: IEEE Standard Logic (2)
  • 10.9: Compilation and Simulation of VHDL Code
  • 10: Problems
  • 10: Chapter Quiz (18)
• Chapter 11: Latches and Flip-Flops
  • 11.1: Introduction (1)
  • 11.2: Set-Reset Latch (3)
  • 11.3: Gated Latches (2)
  • 11.4: Edge-Triggered D Flip-Flop (3)
  • 11.5: S-R Flip-Flop (3)
  • 11.6: J-K Flip-Flop (2)
  • 11.7: T Flip-Flop (4)
  • 11.8: Flip-Flops with Additional Inputs (2)
  • 11.9: Asynchronous Sequential Circuits
  • 11.10: Summary
  • 11: Problems
  • 11: Chapter Quiz (18)
• Chapter 12: Registers and Counters
  • 12.1: Registers and Register Transfers (1)
  • 12.2: Shift Registers (6)
  • 12.3: Design of Binary Counters (1)
  • 12.4: Counters for Other Sequences (9)
  • 12.5: Counter Design Using S-R and J-K Flip-Flops (7)
  • 12.6: Derivation of Flip-Flop Input Equations—Summary
  • 12: Problems
  • 12: Chapter Quiz (18)
• Chapter 13: Analysis of Clocked Sequential Circuits
  • 13.1: A Sequential Parity Checker
  • 13.2: Analysis by Signal Tracing and Timing Charts
  • 13.3: State Tables and Graphs (17)
  • 13.4: General Models for Sequential Circuits (1)
  • 13: Problems
  • 13: Chapter Quiz (19)
• Chapter 14: Derivation of State Graphs and Tables
  • 14.1: Design of a Sequence Detector (2)
  • 14.2: More Complex Design Problems (1)
  • 14.3: Guidelines for Construction of State Graphs (28)
  • 14.4: Serial Data Code Conversion (1)
  • 14.5: Alphanumeric State Graph Notation
  • 14.6: Incompletely Specified State Tables (5)
  • 14: Problems
  • 14: Chapter Quiz (18)
• Chapter 15: Reduction of State Tables State Assignment
  • 15.1: Elimination of Redundant States (3)
  • 15.2: Equivalent States (1)
  • 15.3: Determination of State Equivalence Using an Implication Table (6)
  • 15.4: Equivalent Sequential Circuits
  • 15.5: Reducing Incompletely Specified State Tables (3)
  • 15.6: Derivation of Flip-Flop Input Equations (4)
  • 15.7: Equivalent State Assignments
  • 15.8: Guidelines for State Assignment (2)
  • 15.9: Using a One-Hot State Assignment (3)
  • 15: Problems
  • 15: Chapter Quiz (18)
• Chapter 16: Sequential Circuit Design
  • 16.1: Summary of Design Procedure for Sequential Circuits
  • 16.2: Design Example—Code Converter (5)
  • 16.3: Design of Iterative Circuits (3)
  • 16.4: Design of Sequential Circuits Using ROMs and PLAs (3)
  • 16.5: Sequential Circuit Design Using CPLDs
  • 16.6: Sequential Circuit Design Using FPGAs
  • 16.7: Simulation and Testing of Sequential Circuits
  • 16.8: Overview of Computer-Aided Design
  • 16: Problems
  • 16: Chapter Quiz (18)
• Chapter 17: VHDL for Sequential Logic
  • 17.1: Modeling Flip-Flops Using VHDL Processes (3)
  • 17.2: Modeling Registers and Counters Using VHDL Processes (3)
  • 17.3: Modeling Combinational Logic Using VHDL Processes (8)
  • 17.4: Modeling a Sequential Machine (2)
  • 17.5: Synthesis of VHDL Code
  • 17.6: More About Processes and Sequential Statements
  • 17: Problems
  • 17: Chapter Quiz (18)
• Chapter 18: Circuits for Arithmetic Operations
  • 18.1: Serial Adder with Accumulator (8)
  • 18.2: Design of a Binary Multiplier (5)
  • 18.3: Design of a Binary Divider (4)
  • 18: Problems
  • 18: Chapter Quiz (18)
• Chapter 19: State Machine Design with SM Charts
  • 19.1: State Machine Charts
  • 19.2: Derivation of SM Charts
  • 19.3: Realization of SM Charts (15)
  • 19: Problems
  • 19: Chapter Quiz (18)
• Chapter 20: VHDL for Digital System Design
  • 20.1: VHDL Code for a Serial Adder (3)
  • 20.2: VHDL Code for a Binary Multiplier (2)
  • 20.3: VHDL Code for a Binary Divider
  • 20.4: VHDL Code for a Dice Game Simulator (1)
  • 20.5: Concluding Remarks
  • 20: Problems
  • 20: Chapter Quiz (18)

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